1. Field of the Invention
The present invention relates to a phase-locked loop (PLL) circuit. More particularly, the present invention relates to a PLL circuit in which an output oscillation signal frequency can be controlled based on a bias signal.
2. Description of the Related Art
In general, phase-cocked loop (PLL) circuits are used in various electronic circuits, for example, communication networks. A typical PLL circuit is schematically represented in FIG. 1. This PLL circuit includes a phase comparator 101, a loop filter 102, and a voltage-controlled oscillator (VCO) 103. The phase comparator 101 compares a phase of an input signal Vin with a phase of an output oscillation signal Vosc from the voltage-controlled oscillator 103 to thereby generate a signal corresponding to this phase difference, namely, an error voltage signal Ve. In response to tile error voltage signal Ve, the loop filter 102 generates a control voltage signal Vctr and then applies this control voltage signal to the voltage-controlled oscillator 103. Based on this control voltage signal Vctr, the voltage-controlled oscillator 103 controls a frequency Fosc of the output oscillation signal Vosc. The entire loop constitutes a negative feed-back loop. Thus, this PLL circuit is operable in such a manner that the phase of the output oscillation signal Vosc from the voltage-controlled oscillator 103 is approximated to the phase of the input signal Vin. Accordingly, the output oscillation signal Vosc from the voltage-controlled oscillator 103 is finally synchronized in phase and frequency with the input signal Vin.
FIG. 2 shows a control voltage-oscillation frequency characteristic of the voltage-controlled-oscillator 103. Referring to FIG. 2, in such a case that the control voltage to oscillation frequency characteristic is shown by a characteristic line 50 and also the control voltage Vctr is in a range 50b, frequencies possibly outputted from the voltage-controlled oscillator 103 are in another range 50a. In other words, a frequency range of the input signal Vin in which synchronization can be established in the PLL circuit shown in FIG. 1 is in the range 50a.
Assuming now that an output voltage, namely, the control voltage Vctr from the loop filter 102 when the input signal Vin is not supplied is Vc, a free-running oscillation signal frequency of the voltage-controlled oscillator 103 becomes "Fc0". The free-running oscillation signal frequency Fc of the voltage-controlled oscillator 103 is preferably approximated to the frequency Fin of the input signal Vin. When the frequency Fin of the input signal Vin is preset, it is so designed that the free-running oscillation signal frequency Fc is this preset frequency.
In the above-described PLL circuit shown in FIG. 1, since the characteristic of the voltage-controlled oscillator 103 may be exclusively determined, the frequency range synchronizable with the input signal Vin, e.g., the range 50a in FIG. 2 is necessarily limited. As a consequence, the voltage-controlled oscillator 103 needs be re-designed every time the frequency Fin of the input signal Vin to be synchronized is changed.
Also, there is a case where the characteristics of the voltage-controlled oscillator 103, for example, free-running oscillation frequency Fc and synchronizable frequency range are shifted from the designed values thereof due to fluctuations in the manufacturing processes and/or changes in ambient temperatures of the PLL circuit. In this case, the difference between the free-running oscillation signal frequency Fc and the frequency of the input signal Vin becomes large apart from the designed value. As a result, the time period required until the PLL circuit is synchronized or stabilized would be prolonged, and/or the optimum value of the loop filter would be varied. In the worst case, the frequency of the input signal Vin is out of the synchronizable frequency range of the voltage-controlled oscillator 103, and therefore the synchronization of the PLL circuit can be no longer established.
Referring again to FIG. 2, when the designed value of the control voltage-oscillation frequency characteristic of the voltage-controlled oscillator 103 is shown by a characteristic line 50, the control voltage Vctr is in the range 50b. In this case, the possible oscillation frequency of the voltage-controlled oscillator 103 is in the range 50a, and the free-running oscillation frequency is Fc0. On the other hand, there is a case where the control voltage-oscillation frequency characteristic of the voltage-controlled oscillator 103 is changed due to the manufacturing process variations and the ambient temperature changes. In such a case, when the control voltage-oscillation frequency characteristic of the voltage-controlled oscillator 103 is shifted to be shown by another characteristic line 51, the oscillation frequency is in the range 51a and the free-running oscillation frequency is Fc1. Similarly, when the control voltage-oscillation frequency characteristic of the voltage-controlled oscillator 103 is shifted to be shown by another characteristic line 52, the oscillation frequency is in the range 52a and the free-running oscillation frequency is Fc2.
In this manner, in the conventional PLL circuit, in order to increase the operation reliability thereof, the oscillation signal frequency range of the voltage-controlled oscillator needs be widened based on previous estimation of the manufacturing process fluctuations and the ambient temperature changes during the operation of this PLL circuit. As one conventional range widening method, the gain of the voltage-controlled oscillator is increased, so that the synchronizable frequency range of the input signal to the PLL circuit can be widened. However, this conventional range widening method owns such a problem that the PLL circuit would become sensible to noise and thus jitter would be increased.
On the other hand, when the gain of the voltage-controlled oscillator is increased, the fluctuations in the differences between the free-running oscillation signal frequency Fc and the frequency Fin of the input signal Vin would be increased due to the manufacturing process fluctuations. For this reason, there is a problem in that the optimum values of the loop filters would be greatly changed, depending upon the PLL circuits. As a consequence, the loop filters must be adjusted, depending upon the PLL circuits.
To avoid the above-explained problems, in the PLL circuits disclosed in Japanese Laid Open Patent Disclosure (JP-A-Showa 58-140822) and Japanese Examined Patent Disclosure (JP-B2-Heisei 4-001527), the center frequency, i.e., a free-running oscillation frequency of the voltage-controlled oscillator is fixed by use of a bias current. Also, the gain of the voltage-controlled oscillator is made variable, so that the synchronizable frequency range of the PLL circuit can be widened.
Furthermore, in the PLL circuits disclosed in Japanese Laid Open Patent Disclosure (JP-A-Showa 61-144125 and JP-A-Heisei 6-152401), an adjustment time period is proposed such that the gain of the voltage-controlled oscillator and the free-running oscillation frequency Fc can be set to the designed values or externally inputted values, irrelevant to the manufacturing process fluctuations.
However, the above-described PLL circuits own the following problems. That is, in the former PLL circuits described in JP-A-Showa 58-140822 and JP-A-Heisei 4-001527, the bias current for determining the free-running oscillation frequency is generated by use of resistive elements and transistors. Therefore, when the parameters such as threshold values of transistors and resistance values due to change of manufacturing process parameters are shifted from the designed parameter values, the free-running oscillation frequency Fc and the synchronizable frequency range of the PLL circuit would be shifted from the designed values. In the worst case, there is a risk that the synchronization of these conventional PLL circuits can be no longer established.
Also, in the latter PLL circuits described in JP-A-Showa 61-144125 and JP-A-Heisei 6-152401, adjusting circuits such as a counter and a D/A converter are increased in circuit scale so as to widen the adjustable frequency range and increase the resolution. Accordingly, the overhead of these circuits is not negligible. Also, there is another problem that since the PLL circuits are adjusted in the first stage, the characteristic changes caused by the ambient temperature changes during the circuit operations could not be adjusted.